Cadence Design Systems (India) has entered into an agreement with imec, an independent research centre in nanoelectronics and nanotechnology, in conjunction with the imec Europractice IC Service, to develop a shuttle programme for Cadence University Software Program members. The programme aims to provide Indian universities with access to advanced technologies, enabling their students to work with process and design techniques through to silicon tape-out.
Cadence will offer support to its University Software Program members by providing flows and methodologies, and imec will provide access to IC technologies down to 65nm, SPICE models, design rules, PDKs, and standard cell libraries.
The shuttle programme will allow University Software Program members to tape-out all technologies offered through Europractice. This will give universities foundry access for silicon verification which has been a hurdle due to lack of strong academia-foundry partnerships.
Jaswinder Ahuja, corporate vice president and managing director, Cadence Design Systems (India), said, “The collaboration with imec takes our programme to the next level by giving students access to actual silicon samples. It is an invaluable experience for students to work on a real-life tape out and will better prepare them to handle the tape out pressures of the fast-paced semiconductor industry. The Cadence University Software Program in India currently has more than 250 colleges enrolled across India and encompasses faculty development, the Cadence Design Contest, and the Cadence VLSI Certification Program.”
“From our newly opened Bengaluru office (www.imec-in.in), we look forward to working with Indian universities and companies to validate ideas, build prototypes and support low-volume production. We are very pleased to have the support of Cadence in this endeavour,” said Dr Paul Marchal, R&D director of imec India.
The shuttle programme will allow University Software Program members to tape-out all technologies offered through Europractice. This will give universities foundry access for silicon verification which has been a hurdle due to lack of strong academia-foundry partnerships.
Jaswinder Ahuja, corporate vice president and managing director, Cadence Design Systems (India), said, “The collaboration with imec takes our programme to the next level by giving students access to actual silicon samples. It is an invaluable experience for students to work on a real-life tape out and will better prepare them to handle the tape out pressures of the fast-paced semiconductor industry. The Cadence University Software Program in India currently has more than 250 colleges enrolled across India and encompasses faculty development, the Cadence Design Contest, and the Cadence VLSI Certification Program.”
“From our newly opened Bengaluru office (www.imec-in.in), we look forward to working with Indian universities and companies to validate ideas, build prototypes and support low-volume production. We are very pleased to have the support of Cadence in this endeavour,” said Dr Paul Marchal, R&D director of imec India.
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